Architecture of "Reverse Hash": Neural Networks Without Multiplication

Modern Deep Learning has hit a bottleneck in floating-point computation performance and memory bandwidth. We propose the architecture "Reverse Hash," where the neuron is not a sum of products, but a bit function.

Concept: Neuron as Comparator

Classic neuron: Activation(Sum(Weight * Input))
Our neuron: Output = A[ popcount( Input XOR Mask ) ]

Let's break down the formula:

  1. Input (64 bits): Input data.

  2. Mask (64 bits): The "view" of the neuron. A fixed random pattern.

  3. XOR: Bitwise comparison. 0 - match, 1 - difference.

  4. popcount: Processor instruction (Population Count). Counts the number of ones in a word. This is Hamming Distance - how much the input differs from the mask (a number from 0 to 64).

  5. A [...] (LUT): Response array. This is the memory of the neuron, where its "experience" is stored.

Array A: Evolution from Statistics to Bit

The most important thing is how the array A lives and changes.

1. Training (Accumulation) *Concept

At the training stage, A is an array of counters (for example, uint16 with 65 cells).

  • We present an example.

  • We calculate the distance dist = popcount( Input XOR Mask ).

  • If the example is "useful" - we do A[dist]++.

  • We are simply accumulating a histogram: at what Hamming distance this neuron should activate.

2. Compilation (Threshold)

Training is complete. We turn the "fat" counters into pure logic.
We apply Threshold:

  • If A[i] > threshold - we write 1.

  • Otherwise - 0.

Now the array A is a set of bits. Since there are only 65 indices (from 0 to 64), the entire array A compresses into one 64-bit integer.

3. Inference (Speed)

In working mode, the neuron is two processor registers: Mask and compressed A.
Logic fits into 4 assembly instructions:

  1. XOR (Compare mask and input)

  2. POPCNT (Get distance)

  3. SHIFT (Shift compressed array A by the distance amount)

  4. AND (Take the least significant bit)

No reads from RAM. No FPU. Theoretical performance is limited only by the processor frequency.

P.S.

This is a concept. Right now, the architecture exists in the form of a mathematical model.
The next step here will be a link to Web demo (MNIST 28x28), where you will be able to draw a digit and see the work of XOR neurons in real-time in the browser. (ranked encoding of the input is planned)

But I only have two hands. If you are interested in the topic of Bitwise AI, low-level optimization (JS/WASM/C++) - I would be happy to discuss and help in creating a Proof of Concept. It may require adjustments to the training logic.

Let the bitwise revolution begin!

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